1. Field of the Invention
This invention relates generally to method of manufacturing high density, high performance semiconductor devices that have multiple layers of interconnects. More specifically, this invention relates to a method of manufacturing high density, high performance semiconductor devices that have multiple layers of interconnects that can be filled in a single conductive material filling.
2. Discussion of the Related Art
The increased demand for higher performance semiconductor devices has required the density of metallization lines to be increased and in addition has required the addition of stacked layers. These requirements have necessitated the development of novel approaches in the methods of forming interconnections that not only integrate fine geometry definition but are also conducive to subsequent CMP (chemical mechanical polishing) processing. As the interconnection line widths shrink, the challenges of etching materials using photoresist-as-mask techniques have become increasingly difficult.
Traditional methods of forming interconnection structures include the use of photoresist patterning and chemical or plasma "subtractive" etching as the primary metal-patterning technique. However, using this method, it is not possible to form a planarized layer using conventional dielectric spin-on or fill/etchback techniques for filling in the spaces between the conductive wiring. Therefore, a chemical mechanical polish (CMP) is required to form the planarized surface on which subsequent metallization structures will be built. Additional difficulties in the traditional method include the trapping of impurities or volatile materials, such as aluminum chloride, in the inter-wiring spaces, which may pose reliability risks to the device, leaving residual metal stringers, which may cause electrical shorts, residual photoresist, and poor step coverage. These problems contribute to low yields and necessitate relaxed design rules that result in low layout density.
Previous attempts to address the disadvantage of the traditional etchback methods of providing planarized interconnection structures include a single damascene technique for forming an interconnect or wire. Although the single damascene technique results in improved planarization, the technique is time consuming and requires numerous additional processing steps. In addition, an interface exists between the conductive via and conductive wire that must be dealt with elsewhere.
Another technique utilized to address the disadvantage of the traditional etchback methods is the dual damascene process. The dual damascene process is a two step sequential mask/etch process to form a two level structure such as a via connected to a metal line above the via. Current dual damascene processing technology entails depositing a triple layer sandwich consisting of thick layer of a dielectric material, an etch stop material having a high etch selectivity to the dielectric layer, and a second thick layer of a dielectric material. The two level structure is formed by masking and etching through the top layer of dielectric material and stopping on the layer of etch stop material, etching the etch stop material only, then performing a second masking and etching process with the second mask being an oversize mask. The second etch is to the dielectric material underlying the lower layer of dielectric material. The requirement to perform a second masking and etching process is time consuming and the added processes can be the source of defects in the device being manufactured.
The requirement to manufacture more complex semiconductor devices while maintaining the small size of the devices has resulted in the manufacture of devices that have multiple layers. Because of the complexity of the circuits that are integrated in the devices, it is required for different types of interconnect within layers and between layers. One type of interconnect is completely within a single layer and connects an electrode of a device with an electrode of another device on the same layer. Another type of interconnect is a via that connects an electrode of a device in one layer with an electrode of another device on another layer or with a wire in a metal layer. The via may also connect a wire in one layer with a wire in another layer.
Previous manufacturing methods require mask steps, etch steps and conductive material filling steps to form interconnect structures in each layer. The repetition of each of these steps for each layer is time consuming and has the potential for increasing the number of defects during the manufacturing process.
Therefore, what is needed is a method of manufacturing semiconductor devices having multiple layers in which multiple layers of interconnects can be filled with a conductive material in a single step.